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62707hkim 20070611-s00001 no.a0704-1/26 ver.1.04 lc87f1a32a overview the sanyo lc87f1a32a is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single ch ip a number of hardware features su ch as 32k-byte flash rom (onboard programmable), 2048-byte ram, an onchip debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit pwms), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, two channels of synchronous sio interface (with automatic block transmission/reception capabilities), an asynchronous/synchron ous sio interface, a uart interface (full duplex), a full-speed usb interface (functi on), an 12-bit 12-channel ad converter (1 2- or 8-bit resolutio n selectable), two channels of 12-bit pwm, a system clock frequency divider, an infrared remote controlle r receiver circuit, and a 28- source 10-vector in terrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 3.0 to 5.5v, of voltage source. ? block-erasable in 128 byte units ? writable in 2-byte units ? 32768 8 bits ? ram ? 2048 9 bits ? minimum bus cycle ? 83.3ns (cf=12mhz) note: the bus cycle time here refers to the rom read speed. ordering number : ena0704 cmos ic from 32k byte, ram 2048 byte on-chip 8-bit 1-chip microcontroller with full-speed usb * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc87f1a32a no.a0704-2/26 ? minimum instruction cycle time ? 250ns (cf=12mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1 bit units 28 (p10 to p17, p20 to p27, p30 to p34, p70 to p73, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 4 bit units 8 (p00 to p07) ? usb ports 2 (d+, d-) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for oscillation) 1 (xt1) ? reset pins 1 ( res ) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an-8bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? sio ? sio0: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 512/3 tcyc 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio4: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 1020/3 tcyc 3) automatic continuous data transmission (1 to 2048 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) 4) auto-start-on-falling-edge function 5) clock polarity selectable 6) crc16 calculator circuit built in
lc87f1a32a no.a0704-3/26 ? full duplex uart 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc ? ad converter: 12 bits 12 channels ? 12-/8-bit resolution selectable ad converter ? reference-voltage automatic generation control ? pwm: multifrequency 12-bit pwm 2 channels ? infrared remote controller receiver circuit 1) noise rejection function (noise filter time constant: approx. 120 s when the 32.768khz crystal oscillator is selected as the reference voltage source) 2) supports data encoding systems such as ppm (pulse position modulation) and manchester encoding 3) x'tal hold mode release function ? usb interface (function controller) ? compliant with usb 2.0 full-speed ? supports a maximum of 4 user-defined endpoints. endpoint ep0 ep1 ep2 ep3 ep4 control { - - - - bulk - { { { { interrupt - { { { { transfer type isochronous - { { { { max. payload 64 64 64 64 64 ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) able to output oscillation clock of sub clock. ? interrupts ? 28 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/usb bus acti ve/remote control receive 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/usb bus reset/usb suspend/uart1 receive 8 0003bh h or l sio1/usb endpoint/usb-sof/si o4/uart1 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/pwm0/pwm1 ? priority level: x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence.
lc87f1a32a no.a0704-4/26 ? subroutine stack levels: 1024 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock ? crystal oscillation circuit: for system clock, time-of-day clock ? pll circuit (internal): for usb interface (see fig.5) ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the pll base clock generator , cf, rc and cr ystal oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an bus active interrupt source established in the usb interface circuit ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circ uits except for reception of a remote control signal. 1) the pll base clock generator, cf and rc oscillator automatically stop operation. 2) the state of crystal oscillation established when the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an bus active interrupt source established in the usb interface circuit (6) having an interrupt source established in the infrared remote controller receiver circuit. ? package form ? sqfp48(7 7): ?lead-free type? ? development tools ? on-chip debugger: tcb87 type-b + lc87f1a32a ? flash rom programming boards package programming boards sqfp48(7 7) w87f55256sq ? recommended eprom programmer maker model supported version device flash support group, inc. (single) af9708/af9709/af9709b (including product of ando electric co.,ltd) after rev02.73 lc87f1a32a sanyo skk (sanyo fws) application version: after 1.03 chip data version: after 2.07 lc87f1a32
lc87f1a32a no.a0704-5/26 package dimensions unit : mm (typ) 3163b pin assignment sanyo: sqfp48(7 7) ?lead-free type? p27/int5 p26/int5 p25/int5 p24/int5/sck4 p23/int4/si4/wr p22/int4/so4/rd p21/int4/urx1 p20/int4/utx1 p07/an7/t7o p06/an6/t6o p05/an5/cko p04/an4 p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d- d+ v dd 3 v ss 3 p34/ufilt p33 p32/dbg2 p31/dbg1 p30/dbg0 p70/int0/t0lcp/an8/dpup p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 lc87f1a32a top view sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 11 2 13 24 25 36 37 48
lc87f1a32a no.a0704-6/26 sqfp48 name sqfp48 name 1 p73/int3/t0in/ rmin 25 p04/an4 2 res 26 p05/an5/cko 3 xt1/an10 27 p06/an6/t6o 4 xt2/an11 28 p07/an7/t7o 5 v ss 1 29 p20/int4/utx1 6 cf1 30 p21/int4/urx1 7 cf2 31 p22/int4/so4/ rd 8 v dd 1 32 p23/int4/si4/ wr 9 p10/so0 33 p24/int5/sck4 10 p11/si0/sb0 34 p25/int5 11 p12/sck0 35 p26/int5 12 p13/so1 36 p27/int5 13 p14/si1/sb1 37 d- 14 p15/sck1 38 d+ 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1 41 p34/ufilt 18 pwm0 42 p33 19 v dd 2 43 p32/dbgp2 20 v ss 2 44 p31/ dbgp1 21 p00/an0 45 p30/ dbgp0 22 p01/an1 46 p70/int0/t0lcp/an8/dpup 23 p02/an2 47 p71/int1/t0hcp/an9 24 p03/an3 48 p72/int2/t0in
lc87f1a32a no.a0704-7/26 system block diagram interrupt control from standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer pwm1 timer 6 int0 to 5 noise filte r sio0 port 2 usb pll port 7 port 3 adc sio1 timer 0 timer 1 usb interface timer 7 base timer pwm0 uart1 sio4 on-chip debugger infrared remote controller receive r circuit
lc87f1a32a no.a0704-8/26 pin description pin name i/o description option v ss 1, v ss 2, v ss 3 - - power supply pin no v dd 1, v dd 2 - + power supply pin no v dd 3 - usb reference voltage pin yes port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pins functions ad converter input port: an0 to an7 (p00 to p07) p05: system clock output p06: timer 6 toggle outputs p07: timer 7 toggle outputs yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output/beeper output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p23: int4 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p20: uart1 transmit p21: uart1 receive p22: sio4 date i/o/parallel interface rd output p23: sio4 date i/o/parallel interface wr output p24: sio4 clock i/o interrupt acknowledge type rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable p20 to p27 i/o yes continued on next page.
lc87f1a32a no.a0704-9/26 continued from preceding page. pin name i/o description option port 3 p30 to p34 i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p34: usb interface pll filter pin (see fig.5) onchip debugger pin: dbgp0 to dbgp2 (p30 to p32) yes port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/timer 0l capture input/watchdog timer output/ d+ 1.5k pull-up resistor connect pin p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (input with a noise filter)/timer 0 event input/ timer 0h capture input/ infrared remote controller receiver input ad converter input port: an8(p70), an9(p71) interrupt acknowledge type rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o no pwm0 pwm1 i/o ? pwm0 and pwm1 output port ? general-purpose input port no d- i/o ? usb data i/o pin d- ? general-purpose i/o port no d+ i/o ? usb data i/o pin d+ ? general-purpose i/o port no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? pin functions general-purpose input port ad converter input port: an10 must be connected to v dd 1 if not to be used. no xt2 i/o 32.768khz crystal oscillator output pin ? pin functions general-purpose i/o port ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
lc87f1a32a no.a0704-10/26 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 p20 to p27 p30 to p34 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no d+, d- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal oscillator output (nch-open drain when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). power pin treatment connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. example 1: when the microcontroller is in the backup state in the hold mode, th e power to sustain the high level of output ports is supplied by their backup capacitors. example 2: the high level output at ports is not sustained and unstable in the hold backup mode. v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup lsi lsi v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup
lc87f1a32a no.a0704-11/26 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the activ e/inactive state of reference voltage circuit can be switched by the option select. the procedure for marking the option selection is described below. (1) (2) (3) (4) usb regulator use use use nonuse usb regulator at hold m ode use nonuse nonuse nonuse option select usb regulator at halt mode use nonuse use nonuse normal state active active active inactive hold mode active inactive inactive inactive reference voltage circuit state halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increas e by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference volta ge circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v for backup lsi d+ d- ufilt to usb connector 27 to 33 5pf 0 2.2 f 1.5k p70 v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply 5v for backup lsi d+ d- ufilt 0 2.2 f to usb connector 27 to 33 5pf 1.5k p70 2.2 f 0.1 f
lc87f1a32a no.a0704-12/26 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1, xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ioph(2) pwm0, pwm1 per 1 applicable pin -20 peak output current ioph(3) ports 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 iomh(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 average output current (note 1-1) iomh(3) ports 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 ioah(1) ports 0, 2 total of all applicable pins -25 ioah(2) port 1 pwm0, pwm1 total of all applicable pins -25 ioah(3) ports 0, 1, 2 pwm0, pwm1 total of all applicable pins -45 ioah(4) ports 3 p71 to p73 total of all applicable pins -10 high level output current total output current ioah(5) d+, d- total of all applicable pins -25 iopl(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) ports 3, 7, xt2 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 average output current (note 1-1) ioml(3) ports 3, 7, xt2 per 1 applicable pin 7.5 ioal(1) ports 0, 2 total of all applicable pins 45 ioal(2) port 1 pwm0, pwm1 total of all applicable pins 45 ioal(3) ports 0, 1, 2 pwm0, pwm1 total of all applicable pins 80 ioal(4) ports 3, 7, xt2 total of all applicable pins 15 low level output current total output current ioal(5) d+, d- total of all applicable pins 25 ma allowable power dissipation pd max sqfp48(7 7) ta=-30to+70 c 190 mw operating ambient temperature topr -30 +70 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms.
lc87f1a32a no.a0704-13/26 allowable operating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0.245 s tcyc 200 s 3.0 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.490 s tcyc 200 s except for onboard programming 2.7 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) ports 0, 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 2.7 to 5.5 0.9v dd v dd high level input voltage v ih (3) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side 2.7 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) port 0 pwm0, pwm1 2.7 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer side 2.7 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.245 200 instruction cycle time (note 2-2) tcyc except for onboard programming 2.7 to 5.5 0.490 200 s ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 3.0 to 5.5 0.1 12 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.7 to 5.5 0.1 6 mhz fmcf(1) cf1, cf2 12 mhz ceramic oscillation see fig. 1. 3.0 to 5.5 12 fmcf(2) cf1, cf2 6 mhz ceramic oscillation see fig. 1. 2.7 to 5.5 6 fmrc internal rc oscillation 2.7 to 5.5 0.3 1.0 2.0 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.7 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
lc87f1a32a no.a0704-14/26 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) xt1, xt2 for input port specification v in =v dd 2.7 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.7 to 5.5 15 iil(1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 for input port specification v in =v ss 2.7 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.7 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 p71 to p73 i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (6) pwm0, pwm1 p05 (ck0 when using system clock output function) i oh =-1ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) p00, p01 i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =1ma 2.7 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (8) ports 3, 7 i ol =1ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 2.7 to 5.5 18 50 150 k hysteresis voltage vhys res ports 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf
lc87f1a32a no.a0704-15/26 serial i/o characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig.9. 1 tsckha(1a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? see fig.8. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transmission/reception mode ? usb is in use simultaneous. ? sio4 is not in use simultaneous. ? see fig.8. ? (note 4-1-2) 7 input clock high level pulse width tsckha(1c) sck0(p12) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? see fig.8. ? (note 4-1-2) 2.7 to 5.5 9 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig.8. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tsckha(2b) ? continuous data transmission/ reception mode ? usb is in use simultaneous. ? sio4 is not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(2) +2tcyc tsckh(2) +(19/3) tcyc serial clock output clock high level pulse width tsckha(2c) sck0(p12) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? cmos output selected ? see fig.8. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) +(25/3) tcyc tcyc note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. continued on next page.
lc87f1a32a no.a0704-16/26 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit data setup time tsdi(1) 2.7 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.7 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig.8. 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig.8. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig.8. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) 2.7 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.8. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc87f1a32a no.a0704-17/26 3. sio4 serial i/o characteristics (note 4-3-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(5) 2 low level pulse width tsckl(5) 1 tsckh(5) see fig.8. 1 tsckha(5a) ? usb nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? see fig.8. ? (note 4-3-2) 4 tsckha(5b) ? usb is in use simultaneous. ? do not use sio0 continuous data transmission mode at the same time. ? see fig.8. ? (note 4-3-2) 7 input clock high level pulse width tsckha(5c) sck4(p24) ? usb and continuous data transmission/ reception mode of sio0 are in use simultaneous. ? see fig.8. ? (note 4-3-2) 2.7 to 5.5 10 frequency tsck(6) 4/3 tcyc low level pulse width tsckl(6) 1/2 tsckh(6) ? cmos output selected ? see fig.8 1/2 tsck tsckha(6a) ? usb, aif nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(6) +(5/3) tcyc tsckh(6) +(10/3) tcyc tsckha(6b) ? usb is in use simultaneous. ? do not use sio0 continuous data transmission mode at the same time. ? cmos output selected ? see fig8. tsckh(6) +(5/3) tcyc tsckh(6) +(19/3) tcyc serial clock output clock high level pulse width tsckha(6c) sck4(p24) ? usb and continuous data transmission/reception mode of sio0 are in use simultaneous. ? cmos output selected ? see fig.8. 2.7 to 5.5 tsckh(6) +(5/3) tcyc tsckh(6) +(28/3) tcyc tcyc data setup time tsdi(3) 2.7 to 5.5 0.03 serial input data hold time thdi(3) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input in continuous trans/rec mode, a time from si4run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. continued on next page.
lc87f1a32a no.a0704-18/26 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit serial output output delay time tdd0(5) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.8. 2.7 to 5.5 (1/3)tcyc +0.05 s pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tp1h(1) tp1l(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc tpil(5) rmin(p73) recognized by the infrared remote controller receiver circuit as a signal. 2.7 to 5.5 4 rmck (note 5-1) high/low level pulse width tpil(6) res resetting is enabled. 2.7 to 5.5 200 s note5-1: represents the period of the reference clock (1 tcyc to 128 tcyc or the source frequency of the subclock) for the infrared remote controller receiver circuit.
lc87f1a32a no.a0704-19/26 ad converter characteristics at ta= -30 c to +70 c, v ss 1 = v ss 2 = v ss 3 = 0v <12-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.0 to 5.5 32 115 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a <8-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 20 90 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas: 12-bits ad converter mode: tcad (conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8-bits ad converter mode: tcad (conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc conversion time (tcad)[ s] external oscillator fmcf[mhz] supply voltage range v dd [v] system clock division (sysdiv) cycle time tcyc [ns] ad frequency division ratio (addiv) 12-bit ad 8-bit ad 4.0 to 5.5 1/1 250 1/8 34.8 21.5 12 3.0 to 5.5 1/1 250 1/16 69.5 42.8 note 6-1: the quantization error ( 1/2lsb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
lc87f1a32a no.a0704-20/26 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 9.8 24 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 3.0 to 3.6 5.6 14 iddop(3) 4.5 to 5.5 14 34 iddop(4) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit operation mode ? 1/1 frequency division ration 3.0 to 3.6 7.7 19 iddop(5) 4.5 to 5.5 6.1 14 iddop(6) 3.0 to 3.6 3.7 8.5 iddop(7) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 2.7 to 3.0 3.0 6.7 iddop(8) 4.5 to 5.5 0.63 3.0 iddop(9) 3.0 to 3.6 0.35 1.6 iddop(10) ? fmcf=0mhz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? 1/2 frequency division ration 2.7 to 3.0 0.30 1.3 ma iddop(11) 4.5 to 5.5 39 150 iddop(12) 3.0 to 3.6 17 58 normal mode consumption current (note 7-1) iddop(13) v dd 1 =v dd 2 =v dd 3 ? fmcf=0mhz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? 1/2 frequency division ration 2.7 to 3.0 14 43 a iddhalt(1) 4.5 to 5.5 4.9 12 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 3.0 to 3.6 2.6 6.3 iddhalt(3) 4.5 to 5.5 8.9 23 iddhalt(4) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit operation mode ? 1/1 frequency division ration 3.0 to 3.6 4.6 12 iddhalt(5) 4.5 to 5.5 3.0 7.2 iddhalt(6) 3.0 to 3.6 1.6 3.8 halt mode consumption current (note 7-1) iddhalt(7) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 2.7 to 3.0 1.3 2.9 ma note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc87f1a32a no.a0704-21/26 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(8) 4.5 to 5.5 0.37 1.8 iddhalt(9) 3.0 to 3.6 0.18 0.83 iddhalt(10) ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? 1/2 frequency division ration 2.7 to 3.0 0.15 0.62 ma iddhalt(11) 4.5 to 5.5 24 93 iddhalt(12) 3.0 to 3.6 7.9 33 halt mode consumption current (note 7-1) iddhalt(13) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? 1/2 frequency division ration 2.7 to 3.0 5.8 22 iddhold(1) 4.5 to 5.5 0.08 24 iddhold(2) 3.0 to 3.6 0.03 11 hold mode consumption current iddhold(3) v dd 1 hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.0 0.02 9.6 iddhold(4) 4.5 to 5.5 19 77 iddhold(5) 3.0 to 3.6 5.1 23 timer hold mode consumption current iddhold(6) v dd 1 timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.7 to 3.0 3.3 14 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. usb characteristics and timing at ta = 0c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions min typ max unit high level output v oh(usb ) ? 15k 5% to gnd 2.8 3.6 v low level output v ol(usb) ? 1.5k 5% to 3.6 v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? |(d+)-(d-)| 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 v low level input v il(usb) 0.8 v usb data rise time t r ? r s =27 to 33 ,cl=50pf ? v dd 3=3.0 to 3.6v 4 20 ns usb data fall time t f ? r s =27 to 33 ,cl=50pf ? v dd 3=3.0 to 3.6v 4 20 ns f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2= v ss 3 =0v specification parameter symbol pin conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma tfw(1) ? erase operation 20 30 ms programming time tfw(2) ? write operation 3.0 to 5.5 40 60 s
lc87f1a32a no.a0704-22/26 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator at ta = 0c to +70c circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 6mhz murata cstcr6m00g15l**-r0 ( 39) (39) 680 2.7 to 5.5 0.05 0.50 8mhz murata cstce8m00g15l**-r0 ( 33) (33) 220 3.0 to 5.5 0.05 0.50 10mhz murata cstce10m0g15l**-r0 ( 33) (33) 220 3.0 to 5.5 0.05 0.50 12mhz murata cstce12m0g15l**-r0 ( 33) (33) 330 3.0 to 5.5 0.05 0.50 built-in c1, c2 the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem cl ock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem clock oscillator circuit with a cf oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to 5.5 1.1 3.0 applicable cl value=12.5pf the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd c1 c2 cf cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf rd1
lc87f1a32a no.a0704-23/26 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd gnd internal rc oscillation cf1, cf2 xt1, xt2 operating mode hold reset signal hold reset signal valid tmscf tmsx?tal hold halt
lc87f1a32a no.a0704-24/26 figure 5 external filter circuit for th e internal usb-dedicated pll circuit figure 6 usb port peripheral circuit figure 7 reset circuit c res v dd r res res rd 0 cd 2.2 f p34/ufilt + - when using the internal pll circuit to generate the 48 mhz clock for us b , it is necessary to connect a filter circuit such as that shown to the left to the p34/ufilt pin. 5pf 27 to 33 d- d+ 5pf 27 to 33 1.5k p70 vd3oen note: it?s necessary to adjust the circuit constant of the usb port peripheral circuit each mounting board. make the d+ pull-up resistors available to control on/off according to the vbus. note: determine the value of c res and r res so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the ic's operating voltage.
lc87f1a32a no.a0704-25/26 figure 8 serial i/o waveforms figure 9 pulse input timing signal waveform figure 10 usb data signal timing and voltage level tpil tpih data ram transfer period (sio0, 4 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0, 4 only) t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol
lc87f1a32a no.a0704-26/26 ps this catalog provides information as of june, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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